As transistor device densities continue to increase, minor fabrication and operational defects can have impact transistor operation inversely proportional with the size of the transistor. One of the well-known problems for small field effect transistors is channel hot carrier effects. For example, when a conventional metal oxide semiconductor field effect transistor (MOSFET) structure is scaled down to one micron or less, the potential energy of an electron changes dramatically when it hits the n+ drain boundaries. This sudden change in potential energy in a short distance tends to create a high electric field. This causes the electrons to behave differently within the semiconductor lattice. Electrons which have been activated by high electric fields are referred to as “hot electrons”, and can, for example, penetrate into or through the gate dielectric. Electrons that penetrate into, but not through, the gate dielectric can cause the gate dielectrics to store charge over time, until the transistor ultimately fails.
Several techniques have been proposed to reduce hot carrier effects. One widely used technique is lightly doped drain extension regions, or “LDD” regions, in which a first light implant is performed before sidewall spacers are formed on the gate structure. After the sidewall spacers are in place, a second heavier implant is performed to form source/drain regions. The first implant provides only a relatively low conductivity in the silicon, so that the voltage has a gradient across the LDD region. This gradient helps prevent the voltage difference from appearing entirely at the junction of the drain and channel regions. The LDD region thus provides a region for the voltage gradient to occur, such that the peak electric field is reduced. This tends to reduce channel hot carrier (CHC) effects.
Another conventional technique that has been used is the “double doped drain.” In this technique, for an n-channel transistor, the drain is implanted with both phosphorus and arsenic (or alternatively with both phosphorus and antimony.) Phosphorus diffuses faster, at a given temperature, than arsenic, and thus produces a slightly “fuzzy” drain profile. Again, this has the effect of stretching the voltage change at the drain boundaries, and this reduces the peak electric field, as is desirable.
Another known technique is to employ a thicker sidewall spacer along the edges of the gate structure. For example, after a gate structure has been formed, a further oxidation is commonly performed, to widen the oxide thickness at the lower corners of the gate. This has the effect of slightly increasing the separation between the lower corners of the gate and the silicon substrate. This is usually done, however, primarily to compensate for any damage to the gate dielectric at the lower gate corners that may be caused by etching processes.